The present invention relates to a demodulation device and, more particularly, to a demodulation device having an improved timing signal generating means for sampling and converting a demodulated baseband signal to a digital signal in a digital carrier transmission system.
In a conventional demodulation device in a digital carrier transmission system, a sampling timing signal having a prescribed period and timing phase is required to sample and convert the demodulated baseband signal to a digital signal. A timing synchronizing circuit is conventionally used to generate the timing signal for extracting a predetermined timing signal from the demodulated baseband signal.
FIG. 1 shows a four-phase modulated signal demodulation device of the related art. Reference symbol S denotes an input terminal of the four-phase modulated signal. The input terminal S is connected to the input terminals of two phase detectors 1 and 2. The control terminals of the phase detectors 1 and 2 are connected to an output of a voltage-controlled oscillator 40 directly and through a .pi./2 phase shifter 3, respectively. The output terminals of the phase detectors 1 and 2 are connected to the input terminals of 2-bit A/D converters 4 and 5 and full-wave rectifiers 7 and 8, respectively. The output terminals of the full-wave rectifiers 7 and 8 are connected to the input terminals of timing synchronizing circuits 14 and 15. Two output signals from the 2-bit A/D converters 4 and 5 are supplied to a carrier regenerating circuit 6. The output of the carrier regenerating circuit 6 is supplied to the voltage-controlled oscillator 40.
The timing synchronizing circuit 14 has the same arrangement as the timing synchronizing circuit 15. The timing synchronizing circuit 14 comprises a voltage-controlled oscillator 13, a phase comparator 11 for comparing a phase of the output of the full-wave rectifier 7 with that of the voltage-controlled oscillator 13, and a low-pass filter 12 for receiving the output of the phase comparator 11 to control the output of the voltage-controlled oscillator 13. The output of the voltage-controlled oscillator 13 is supplied to a phase adjusting circuit 9. The output terminal of the phase adjusting circuit 9 is connected to the control terminal of the 2-bit A/D converter 4.
The full-wave rectifier 8, the 2-bit A/D converter 5, a phase adjusting circuit 10 and the timing synchronizing circuit 15 are connected in the same manner as described above.
A 4-phase PSK (phase shift keying) carrier wave is supplied to the input terminal S and is branched and supplied to the phase detectors 1 and 2. Upon reception of a control signal (i.e., an error signal) from the carrier regenerating circuit 6, the voltage-controlled oscillator 40 generates a carrier regenerating signal having a predetermined phase. This carrier regenerating signal is supplied to the phase detector 1 directly and to the phase detector 2 through the .pi./2 phase shifter 3, as respective reference signals which have a phase difference of .pi./2 radian to each other. The phase detectors 1 and 2 detect the branched 4-phase PSK carrier wave in accordance with the reference signals and supply binary baseband signals to the 2-bit A/D converters 4 and 5, respectively. The binary baseband signals are also supplied to the full-wave rectifiers 7 and 8, respectively. The full-wave rectifiers 7 and 8 double the frequency of the binary baseband signals to extract timing signals, respectively. These extracted timing signals are supplied to the timing synchronizing circuits 14 and 15, respectively. The operation of the timing synchronizing circuit 14 is the same as that of the timing synchronizing circuit 15, so that the operation is exemplified only by the timing synchronizing circuit 14.
The extracted timing signal from the full-wave rectifier 7 is supplied to the phase comparator 11 in the timing synchronizing circuit 14. The phase comparator 11, the low-pass filter 12 and the voltage-controlled oscillator 13 constitute a phase synchronizing loop. The voltage-controlled oscillator 13 generates a regenerated timing signal which is synchronized with the phase of the extracted timing signal. The jitter component of the regenerated timing signal is suppressed by an equivalent narrow-band filter characteristic. The regenerated timing signal is supplied to the phase adjusting circuit 9 whose output is then supplied to the control terminal of the 2-bit A/D converter 4. Similarly, the timing synchronizing circuit 15 regenerates a timing signal. The jitter component of this regenerated signal is also suppressed in accordance with the extracted timing signal supplied from the full-wave rectifier 8 in the same manner as described above. The regenerated signal is adjusted by the phase adjusting circuit 10. The phase-adjusted timing signal is thus supplied from the phase adjusting circuit 10 to the control terminal of the 2-bit A/D converter 5.
In the 2-bit A/D converters 4 and 5, the binary baseband signals supplied from the phase detectors 1 and 2 are sampled in response to the regenerated timing signals supplied through the phase adjusting circuits 9 and 10, respectively. The A/D converters 4 and 5 then generate data signals X1 and Y1, respectively. Data signals X2 and Y2 in addition to the data signals X1 and Y1 are generated by the 2-bit A/D converters 4 and 5, respectively. The data signals X1, X2, Y1 and Y2 are supplied to the carrier regenerating circuit 6. An error signal is generated by the carrier regenerating circuit 6 to control the voltage-controlled oscillator 40, so that a predetermined carrier regenerating signal is generated. This signal is branched and supplied to the phase detectors 1 and 2 directly and through the .pi./2 phase shifter 3, respectively. The operation of the carrier wave regenerating circuit 6 is well known to those skilled in the art, as described in Japanese Patent Published No. 57-131151.
In the conventional demodulation device described above, the output signals of the timing synchronizing circuits 14 and 15 must be adjusted by means of the phase adjusting circuits 9 and 10 so that the demodulated baseband signal is sampled by the 2-bit A/D converters 4 and 5 at optimal timings, resulting in inconvenience.